|Type of Certificate
|General purpose microprocessor IP including safety features
|ARM Cortex-R52+ Processor IP Core
Approved versions, see current Revision List
|Codes and Standards
|Scope and Result
|The ARM Cortex-R52+ Processor IP Core complies with the requirements of
IEC 61508 for SIL 3 regarding the avoidance of systematic faults for a Compliant
Item and complies with the requirements of ISO 26262 for ASIL D regarding the
avoidance of systematic faults for a Safety Element out of Context (SEooC).
Based on an exemplary configuration, ARM showed that the target values for the
random hardware fault metrics according ISO 26262-5, Clauses 8 and 9
for ASIL D can be met. As a result, the Cortex-R52+ Processor can be used in
safety-related applications up to SIL3 according to IEC 61508 and up to ASIL D
according to ISO 26262.
|The requirements and constraints mentioned in the Cortex-R52+ Safety Manual have to be taken into account by the user.
|no expiry date
Remark: In case of missing entries this is due to restrictions by the certificate holder